wafer.space Community - [0.5x0.5 changes] 🧵

https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/17

[quarter slot] Update PCB by Essenceia · Pull Request #17 · wafer...

Changes made: rotate design to have pin 1 on the bottom left. make boards 4 layers use 2 additional layers for providing better ground add an arrow in the opposite corner to pin 1 to match the ...

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2:11 a.m.

Added teardrops while I was at it.

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Essen

Added teardrops while I was at it.

This is wonderful! Thank you!

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Andrew Wingate

This is wonderful! Thank you!

Thanks. Hit me up if the annular ring DFM checks give you trouble, I have kept the same vias but there are quite skinny.

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Thank you @Essen! I was looking at this board while working on the others earlier, and made a few small tweaks - mainly trying to get the ground connections as good as possible. I've just put a small PR up: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/19 If you have chance, it would be great to get your yay/nay on that before Andrew merges

Some small tweaks to quarter slot CoB by MichaelBell · Pull Reques...

A few small tweaks to power and ground connections: Thickened up a few ground/power connections to 0.2mm, given the minimum trace separation can be reduced to 0.1mm (as we're using 4 layer...

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RebelMike

Thank you @Essen! I was looking at this board while working on the others earlier, and made a few small tweaks - mainly trying to get the ground connections as good as possible. I've just put a small PR up: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/19 If you have chance, it would be great to get your yay/nay on that before Andrew merges

Thanks Mike, I will get back to you in under 24 hours.

RebelMike

Thank you @Essen! I was looking at this board while working on the others earlier, and made a few small tweaks - mainly trying to get the ground connections as good as possible. I've just put a small PR up: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/19 If you have chance, it would be great to get your yay/nay on that before Andrew merges

Looks good to me.

Thanks for keeping the teardrops.

RebelMike

Thank you @Essen! I was looking at this board while working on the others earlier, and made a few small tweaks - mainly trying to get the ground connections as good as possible. I've just put a small PR up: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/19 If you have chance, it would be great to get your yay/nay on that before Andrew merges

My only nit would be for incorporating tnt's comment on annular ring, so I made a PR with that change based on your PR and will let you merge if you agree. https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/20 (edited)

[quarter slot] annular ring on start end layers only by Essenceia ...

Change based on tnt's comment: This PR is a child to @MichaelBell change: Some small tweaks to quarter slot CoB #19

Great, thanks. Yes, I’ll make that change in the others too (if Andrew hasn’t already!)

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I've not used this setting before. I notice that on the 1x1 where Andrew made the change, the ground vias have kept their annular rings on the inner layers (and in the pcb file there's (zone_layer_connections "In1.Cu" "In2.Cu")), but in your change to the quarter slot they are gone and no vias have those zone layer connections listed. Similarly if I set annular rings to start, end and connected then I lose the inner layer rings. I don't think this is actually important because the ground flood on the inner layers goes right through the vias, but I'm not 100% sure and it is weird.

RebelMike

I've not used this setting before. I notice that on the 1x1 where Andrew made the change, the ground vias have kept their annular rings on the inner layers (and in the pcb file there's (zone_layer_connections "In1.Cu" "In2.Cu")), but in your change to the quarter slot they are gone and no vias have those zone layer connections listed. Similarly if I set annular rings to start, end and connected then I lose the inner layer rings. I don't think this is actually important because the ground flood on the inner layers goes right through the vias, but I'm not 100% sure and it is weird.

( If I understand your comment correctly ) I believe losing the annular ring on via unconnected to the inner layers is normal. (edited)

11:16 p.m.

but in your change to the quarter slot they are gone and no vias have those zone layer connections listed

I am less familiar with the kicad file structure, but I expect the gnd vias to still all still be connected to the inner GND fill zones just as in Andrew's changes.

11:18 p.m.

I did forget to re-fill the zones so I just pushed a new commit, not sure if that wasn't the cause. (edited)

11:19 p.m.

Inner layer GND connection:

Ah hah, looks like that’s fixed it. Thanks!

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Cool, nice catch

We really should set up GitHub actions to run DRC/ERC checks on pull requests (and also do a reflood of regions and verify no diffs). Potentially it could even do preview renders or visual diffs type thing? I know I have seen actions which do that type of thing but do not know what the current best practices are.

So we cannot have anything reflood as the panels would get all screwed up unfortunately

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Tim 'mithro' Ansell

We really should set up GitHub actions to run DRC/ERC checks on pull requests (and also do a reflood of regions and verify no diffs). Potentially it could even do preview renders or visual diffs type thing? I know I have seen actions which do that type of thing but do not know what the current best practices are.

That would be very useful indeed.

Andrew Wingate

So we cannot have anything reflood as the panels would get all screwed up unfortunately

Is this because the panels would be bent by the heat of the reflow process or is there something else ? Also, when you mean anything, do you mean anything ? Does this mean cms are a no go and we need to rethink how we do the connector ?

Essen

Is this because the panels would be bent by the heat of the reflow process or is there something else ? Also, when you mean anything, do you mean anything ? Does this mean cms are a no go and we need to rethink how we do the connector ?

it's because the reflood would not honor the board edges (because edge.cuts is not board outline anymore) so all individual boards would flood together and not honor clearances demanded by jlc and others for flood to v-cut

Andrew Wingate

it's because the reflood would not honor the board edges (because edge.cuts is not board outline anymore) so all individual boards would flood together and not honor clearances demanded by jlc and others for flood to v-cut

I have to admit I might not quite follow what the link between reflow (maybe reflood != reflow, in which case I don't know what reflood is) and the v-cut clearance, but if I get what you are saying is that there isn't enough clearance between each board edge ? Is the connector footprint the one that is to close to the edge and causing the DFM violation ? (edited)

2:38 a.m.

What should the new clearance be ?

reflood == pouring the ground plane in KiCad

Andrew Wingate

reflood == pouring the ground plane in KiCad

Ah got it, my bad.

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Andrew Wingate

reflood == pouring the ground plane in KiCad

Hum, I allways assumed that the flood zone (calling it that to be inline with the conversation flow) are defined per there own coordinate set and not inherited from the board cut

So how are you creating the gnd planes during penalization ? Do you have to re-draw them all by hand ? (edited)

Essen

Hum, I allways assumed that the flood zone (calling it that to be inline with the conversation flow) are defined per there own coordinate set and not inherited from the board cut

So how are you creating the gnd planes during penalization ? Do you have to re-draw them all by hand ? (edited)

append the board and do not re-pour

Andrew Wingate

append the board and do not re-pour

So the pannelized boards have no filled gnd plane ?

2:53 a.m.

To confirm, because if that is the case I will want to add a lot more gnd connections on the pcb.

Essen

So the pannelized boards have no filled gnd plane ?

take the board you made as example. You have poured planes. They persist, but when you add (many) to a panel (and remove the edge.cuts shape this may be where you're getting lost) you cannot re-pour Does that make sense>

Andrew Wingate

So we cannot have anything reflood as the panels would get all screwed up unfortunately

I'm pretty sure you can mark the flood regions edges and proper keep outs? (edited)

I think there's ways around this, I'm not certain how much you gain in all this anyways, because any change to the child can't just be pushed and must be redone.

Andrew Wingate

take the board you made as example. You have poured planes. They persist, but when you add (many) to a panel (and remove the edge.cuts shape this may be where you're getting lost) you cannot re-pour Does that make sense>

I am sorry, but I am still very confused. To my understanding edge cuts and fill zones are different things. I can remove edge cuts and keep fill zones. So I guess you have another problem I am not seeing. Example of what I mean with the edge cut very far from the fill zone limits :

*clearances

3:02 a.m.

if you put edge.cuts on there you will see the pour change

3:02 a.m.

see the zone here

Ah yes, I see it, see leftmost. Example with the worlds most ugly pannelization work (proof that you should never count on me to do the pannelization) So you just want us to un-pour all zones ? (edited)

3:04 a.m.

3:06 a.m.

Interesting tid bit, I had not thought about it.

I think @Essen got the wrong end of the stick here and has cleared the floods on the CoB. The point is that after panelization you can’t re-flood. We do want the zones built on the individual CoBs before they are panelized. So don’t take the last commit on PR20.

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